1. Field of the Invention
The present invention relates to an E/D integrated circuit obtained by connecting a depletion field effect transistor serving as a load and an enhancement field effect transistor serving as a switching transistor in series with each other and, more particularly, to an improvement of the performance of the E/D integrated circuit when it is formed in a compound semiconductor substrate.
2. Description of the Related Art
As an E/D circuit obtained by connecting a depletion field effect transistor (to be referred to as a D-type FET or a D-type MESFET hereinafter) serving as a load and an enhancement field effect transistor (to be referred to as an E-type FET or an E-type MESFET hereinafter) serving as a switching transistor in series with each other, an E/D inverter is widely known.
In a conventional method, in order to add a parasitic capacitance to an E/D inverter or the like, a gate length and a gate width generally have minimum dimensions. This is a condition which is necessarily required for an E-type FET serving as a switching transistor requiring a high-speed operation. In a D-type FET serving as a load, this condition is satisfied. Therefore, the gate lengths of the D-type FET serving as a load and the E-type FET serving as a switching transistor are equal to each other.
However, in minimum dimensions, i.e., in a range of a gate length obtained by the most advanced process, a threshold voltage of an FET largely varies. This case is shown in FIG. 1. FIG. 1 is a view schematically showing a relationship between the gate length and threshold voltage of a transistor. As shown in FIG. 1, in a range r of a gate length obtained by the most advanced process, a threshold value largely varies due to small process fluctuations. Especially in an E/D inverter, when the threshold voltage of a D-type FET serving as a load varies, a current supplied to an E-type FET serving as a switching transistor connected in series with the D-type FET varies. When a current supplied to the E-type FET varies, a variation in output voltage or the like is caused, and the performance serving as the switching circuit is degraded. Since a process technique is not sufficiently established especially in a GaAs IC/LSI, a variation in threshold value of the GaAs IC/LSI due to process fluctuations is larger than that of a silicon IC/LSI. For this reason, in the GaAs IC/LSI, a circuit design capable of absorbing the process fluctuation is desired.